(a) Field of the Invention
The invention relates to a first in first out device (FIFO) device, particularly to first in first out device (FIFO) device, crossing different power domains.
(b) Description of the Related Art
In digital circuits, clock signals are used to define clock reference of data flow in circuits and, in order to have each element driven by the clock signal in the circuit receive the clock signal, generally a clock tree is generated from one point of the clock signal or its source to be used by the internal elements of an integrated circuit (hereinafter referred to as “IC”). But, there is delay between the clock signals before and after the clock tree is generated to result in necessity of correspondingly adjusting data hold time.
Accompanying with the rise of environmental protection consciousness, if an IC is under power down or power saving, low power consumption of the IC is critically required and the solution based on the current technology is to divide the IC into different power domains. As shown in FIG. 1A, the IC is divided into three different power domains PD1˜PD3 and the power domains PD1˜PD3 have corresponding power sources P1˜P3. Under power down or power saving, only the power domain for executing enabling and the corresponding power source are remained to minimize power consumption.
Please refer to FIG. 1B. FIG. 1B shows part of the circuit different power domains. As shown in FIG. 1B, 10 and 11 each represent a virtual buffer or a delay unit to show the delay generated between a source clock and the clock tree generated by the source clock. It should be noted that the buffers or delay units 10 and 11 are expression of delay only but not actual buffers or delay units. The actual buffer of the clock tree is not labeled.
The source end (power domain PD1) in FIG. 1B is provided with an input register 13 to receive an input signal In driven by the first clock signal TC1 generated by the source clock SC through the delay unit 10. The data of the input signal In is transmitted from the input register 13 to the output register 15 at the back end and an output signal Out is outputted. The circuits of the first clock signal TC1 and the second clock signal TC2 outputted by the delay units 10 and 11 are generated by clock tree synthesis. An ideal first clock signal TC1 and an ideal second clock signal TC2 are substantially the same (substantially line-up, or said, TC1 and TC2 have the same phase), shown in the timing diagram of the bottom of FIG. 1B.
However, even though the voltage of different power domains is designed to be the same, the power consumption of each different power domain is still actually different and the voltage of the each power domain has different voltage drop so that the clock tree has different delay time variation. As shown in FIG. 1C, a schematic diagram having the above problem is shown. (Since data transmission still exists in different power domains, the power consumption of a different power domain is different even for synchronous data transmission. In terms of the circuits are operated under different power domains, the delay time would also be changed and different on the clock tree even if it is a synchronous system. From the timing diagram shown at the bottom of FIG. 1C, it can be understood that the voltage supplied by the power domain PD1 is higher than that by the power domain PD2 to have the first clock signal TC1 is faster than the second clock signal TC2, at the location circled by the dashed line, to generate hold time violation.
On the contrary, please refer to FIG. 1D. From the timing diagram shown at the bottom of FIG. 1D, it can be understood that the voltage supplied by the power domain PD2 is higher than that by the power domain PD1 to have the second clock signal TC2 is faster than the first clock signal TC1, at the location circled by the dashed line, to generate set up time violation.